1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a method of forming an electrically insulating material with a low dielectric constant and good mechanical strength and a structure including a dielectric having low dielectric constant and good mechanical strength.
2. Discussion of Related Art
In 1965, Gordon Moore first observed that the number of transistors per unit area on an IC chip doubled approximately every 18 months. Over the ensuing decades, the semiconductor industry has managed to adhere to the schedule projected by the so-called Moore's Law for improving the device density.
The transistors on the chip are usually fabricated in a substrate from a semiconductor material, such as Silicon, and an electrically insulating material, such as Silicon Oxide or Silicon Nitride. Subsequently, the transistors are wired with an electrically conducting material, such as Aluminum or Copper. The electrically conducting material may be stacked in multiple layers that are separated by the electrically insulating material.
Maintaining the schedule for each device generation or technology node has required continual enhancements to the processes of photolithography and etch to reduce the critical dimension (CD) that may be successfully patterned in the features across the chip. In addition, significant improvements had to be made to the processes of ion implantation, oxidation, and deposition to produce the desired doping levels and film thicknesses across the chip.
Photolithography was able to keep up with the reduction in CD needed for each device generation. However, improving the resolution that could be achieved often required sacrificing the depth of focus (DOF) that could be tolerated. As a result, the smaller DOF had to be countered by reducing the topography at the surface of the substrate in which the device was being formed. Planarization of the surface of the substrate became necessary to reduce topography for both the front-end and the back-end of semiconductor processing. Chemical-mechanical polish (CMP) is an enabling technology to planarize advanced devices.
In order to improve device density, both the transistor in the front-end of semiconductor processing and the wiring in the back-end of semiconductor processing have to be scaled down. The scaling of the transistor and the scaling of the wiring must be carefully balanced to prevent limitation of the switching performance. The switching performance of the transistor may be degraded by excessively large resistance-capacitance (RC) product delay in the wiring. Resistance in the wiring may be reduced by using an electrically conducting material with a lower resistivity. Capacitance in the wiring may be reduced by using an electrically insulating material with a lower dielectric constant (k).
However, an electrically insulating material with a low dielectric constant may not be strong enough to withstand CMP.
Thus, what is needed is a method of forming an electrically insulating material with a low dielectric constant and good mechanical strength and a structure including a dielectric having low dielectric constant and good mechanical strength.